1. Field
The present description relates to integrated circuit packaging, and more particularly, to bypass capacitor design and placement on an integrated circuit package.
2. Background
IC's (Integrated Circuits) are manufactured in and on semiconductor wafers with several layers of active circuitry. The wafer is cut into separate semiconductor chips which are mounted to and electrically coupled to package substrates. The package substrates have several layers including a ground plane, and a power plane. The package substrates are sealed inside a package from which pins for the ground plane, power plane and active circuitry extend. These pins allow the package to be coupled to a PCB (Printed Circuit Board).
At higher clock speeds (for example higher than 1 GHz) and faster clock signal rise times (for example less than 100 psec), the power delivery design of integrated circuit packages, results in a very high loop inductance. The loop inductance of the power delivery system may be reduced using bypass capacitors. Bypass (decoupling) capacitors are also used to reduce electrical noise and to suppress unwanted radiation. The electrical noise is generated by capacitive and inductive parasitics and by the continuous switching of the transistors in the circuit.
One type of bypass capacitor is an ECC (Embedded chip capacitor). ECC's are placed on power-consuming circuits and are able to smooth out voltage variations using the stored charge on the decoupling capacitor. The stored charge is used as a local power supply to device inputs during signal switching stages, allowing the decoupling capacitor to mitigate the effects of voltage noise induced into the system by parasitic inductance. However, such decoupling capacitors use space on the chip that might otherwise be used for additional circuitry. In addition, such decoupling capacitors are complex to build within the chip's circuitry. They reduce system yield, and increase production costs. They also suffer from significant voltage leakage increasing heat and power consumption for the chip.
Bypass capacitors may also be placed on both the bottom side of the exterior of an integrated circuit package directly underneath the die (land side capacitor) and on the top side of the exterior of the package (die side capacitor). With land side capacitors, the capacitors' terminals are connected to IC loads through the package substrate. Electrically conductive vias and patterned planes within the package substrate allow the capacitors to provide bypassing capacitance to the IC.
Connection of the capacitors to the load through the vias and planes results in some “vertical” inductance, also referred to as “loop” inductance, in the supply and return via loop between each capacitor and the integrated circuit load. Land side capacitors in a typical package are located on the same side of the package as the power and data connection pins or pads for the package. As a result, the capacitors can interfere with the pins or pads on the bottom side of surface mounted components.
Die side capacitors, mounted on the opposite side from the connection pins and pads do not interfere with mounting the package. However, die side capacitors have still higher inductance characteristics. In addition, since die side capacitors attach to the metal layers of the IC, the total number of capacitors is limited by the amount of metal available on the surface of the die.
Both land side and die side capacitors require surface area on the package that then cannot be used for any other purpose. As IC's become smaller, less surface area is available for mounting capacitors. Even as packages grow smaller some space is still required for handling the package and for pressing it into sockets for burn-in, test, and installation. Handling and pressing a package risks damaging or dislodging any nearby capacitors.